Symmetric Interconnection Networks from Cubic Crystal Lattices

Torus networks of moderate degree have been widely used in the supercomputer industry. Tori are superb when used for executing applications that require near-neighbor communications. Nevertheless, they are not so good when dealing with global communications. Hence, typical 3D implementations have evolved to 5D networks, among other reasons, to reduce network distances. Most of these big systems are mixed-radix tori which are not the best option for minimizing distances and efficiently using network resources. This paper is focused on improving the topological properties of these networks. By using integral matrices to deal with Cayley graphs over Abelian groups, we have been able to propose and analyze a family of high-dimensional grid-based interconnection networks. As they are built over $n$-dimensional grids that induce a regular tiling of the space, these topologies have been denoted \textsl{lattice graphs}. We will focus on cubic crystal lattices for modeling symmetric 3D networks. Other higher dimensional networks can be composed over these graphs, as illustrated in this research. Easy network partitioning can also take advantage of this network composition operation. Minimal routing algorithms are also provided for these new topologies. Finally, some practical issues such as implementability and preliminary performance evaluations have been addressed

Classes of Symmetric Cayley Graphs over Finite Abelian Groups of Degrees 4 and 6

The present work is devoted to characterize the family of symmetric undirected Cayley graphs over finite Abelian groups for degrees 4 and 6.Comment: 12 pages. A previous version of some of the results in this paper where first announced at 2010 International Workshop on Optimal Interconnection Networks (IWONT 2010). It is accessible at http://upcommons.upc.edu/revistes/handle/2099/1037

Network unfairness in dragonfly topologies

Dragonfly networks arrange network routers in a two-level hierarchy, providing a competitive cost-performance solution for large systems. Non-minimal adaptive routing (adaptive misrouting) is employed to fully exploit the path diversity and increase the performance under adversarial traffic patterns. Network fairness issues arise in the dragonfly for several combinations of traffic pattern, global misrouting and traffic prioritization policy. Such unfairness prevents a balanced use of the resources across the network nodes and degrades severely the performance of any application running on an affected node. This paper reviews the main causes behind network unfairness in dragonflies, including a new adversarial traffic pattern which can easily occur in actual systems and congests all the global output links of a single router. A solution for the observed unfairness is evaluated using age-based arbitration. Results show that age-based arbitration mitigates fairness issues, especially when using in-transit adaptive routing. However, when using source adaptive routing, the saturation of the new traffic pattern interferes with the mechanisms employed to detect remote congestion, and the problem grows with the network size. This makes source adaptive routing in dragonflies based on remote notifications prone to reduced performance, even when using age-based arbitration.Peer ReviewedPostprint (author's final draft

Symmetric L-graphs

In this paper we characterize symmetric L-graphs, which are either Kronecker products of two cycles or Gaussian graphs. Vertex symmetric networks have the property that the communication load is uniformly distributed on all the vertices so that there is no point of congestion. A stronger notion of symmetry, edge symmetry, requires that every edge in the graph looks the same. Such property ensures that the communication load is uniformly distributed over all the communication links, so that there is no congestion at any link.Peer Reviewe

Analysing Mechanisms for Virtual Channel Management in Low-Diameter networks

To interconnect their growing number of servers, current supercomputers and data centers are starting to adopt low-diameter networks, such as HyperX, Dragonfly and Dragonfly+. These emergent topologies require balancing the load over their links and finding suitable non-minimal routing mechanisms for them becomes particularly challenging. The Valiant load balancing scheme is a very popular choice for non-minimal routing. Evolved adaptive routing mechanisms implemented in real systems are based on this Valiant scheme. All these low-diameter networks are deadlock-prone when non-minimal routing is employed. Routing deadlocks occur when packets cannot progress due to cyclic dependencies. Therefore, developing efficient deadlock-free packet routing mechanisms is critical for the progress of these emergent networks. The routing function includes the routing algorithm for path selection and the buffers management policy that dictates how packets allocate the buffers of the switches on their paths. For the same routing algorithm, a different buffer management mechanism can lead to a very different performance. Moreover, certain mechanisms considered efficient for avoiding deadlocks, may still suffer from hard to pinpoint instabilities that make erratic the network response. This paper focuses on exploring the impact of these buffers management policies on the performance of current interconnection networks, showing a 90\% of performance drop if an incorrect buffers management policy is used. Moreover, this study not only characterizes some of these undesirable scenarios but also proposes practicable solutions

High-Performance, Low-Complexity Deadlock Avoidance for Arbitrary Topologies/Routings

Recently, the use of graph-based network topologies has been proposed as an alternative to traditional networks such as tori or fat-trees due to their very good topological characteristics. However they pose practical implementation challenges such as the lack of deadlock avoidance strategies. Previous proposals are either exceedingly complex, underutilise network resources or lack flexibility. We propose- and prove formally- three generic, low-complexity dead-lock avoidance mechanisms that only require local information. The main strengths of our method are its topology- and routing- independence and that the virtual channel count is bounded by the length of the longest path. We evaluate our proposed mechanisms against previous proposals through an extensive simulation study to measure the impact on the performance using both synthetic and realistic traffic. First we compare against a well-known HPC mechanism for dragonfly and achieved similar performance level. Then we moved to Graph-based networks and show that our mechanisms can greatly outperform traditional, spanning-tree based mechanisms, even if these use a much larger number of virtual channels. Overall, we find that our proposal provides a simple, flexible and high performance deadlock-avoidance solution

Tecnología low-cost para motivar al alumno

La docencia en Estructura y Organización de Computadores se imparte habitualmente utilizando una arquitectura como referencia, siendo MIPS una de las más usadas. Sin embargo, su baja penetración en el mercado actual tiene un efecto desmotivador en los alumnos. Esto, junto con la mayor relevancia de la arquitectura ARM, nos ha hecho plantearnos considerarla como referencia en nuestros planes de estudios. Con este objetivo, se ha desarrollado un proyecto de innovación docente para rediseñar las materias implicadas. Esta modificación ha implicado cambios en el laboratorio en el que se desarrollan las prácticas, para el que se ha seleccionado Raspberry Pi, una plataforma de bajo coste basada en ARM. Como principal diferencia respecto a otras soluciones, se ha elegido el sistema operativo RISC OS, que permite realizas prácticas de programación en ensamblador y Entrada/Salida en el mismo entorno. Además, se ha desarrollado un depurador en ARM llamado !UCDebug. En este artículo se describen las diferentes etapas del proyecto y los resultados obtenidos. Cabe destacar que, en los dos cursos que lleva implantado, la motivación y asistencia de los alumnos ha aumentado considerablemente y la tasa de éxito ha subido hasta un 13%.Computer Organization and Design is usually instructed using a computer architecture as reference. The MIPS architecture has been traditionally widespread in that regard. However, its current low market share discourages the students. This, coupled with the greater relevance of the ARM architecture, has motivated our switch to the latter as the reference in our degree. With this aim, a redesign of the involved courses has been carried out through an educational innovation project. One of the effects has been a transition to the low-cost ARM Raspberry Pi platform for the computer lab where students perform their practical sessions. As a major difference to the approach followed by other universities, the RISC Operating System has been chosen, allowing to perform both assembly and Input/Output practices within the same environment. Moreover, an ARM debugger called !UCDebug has been developed to alleviate the lack of user-friendly debugging tools. This article describes the stages of the project and the results achieved. Notably, student motivation and attendance has remarkably risen, and the success rate has grown up to 13% since the implementation.Este trabajo ha sido parcialmente financiado por la III Convocatoria de Proyectos de Innovación Docente, del Vicerrectorado de Ordenación Académica y Profesorado de la Universidad de Cantabria, el Ministerio de Economía, Industria y Competitividad bajo contrato TIN2016-76635-C2-2-R (AEI/FEDER, UE) y el Ministerio de Ciencia, Innovación y Universidades bajo beca Juan de la Cierva FJCI-2017-31643